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<title>MFENCE—Memory Fence </title></head>
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<h1>MFENCE—Memory Fence</h1>
<table>
<tr>
<th>Opcode</th>
<th>Instruction</th>
<th>Op/En</th>
<th>64-Bit Mode</th>
<th>Compat/Leg Mode</th>
<th>Description</th></tr>
<tr>
<td>0F AE F0</td>
<td>MFENCE</td>
<td>NP</td>
<td>Valid</td>
<td>Valid</td>
<td>Serializes load and store operations.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>NP</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows the MFENCE instruction.<sup>1</sup> The MFENCE instruction is ordered with respect to all load and store instructions, other MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID instruction). MFENCE does not serialize the instruction stream.</p>
<p>Weakly ordered memory types can be used to achieve higher processor performance through such techniques as out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store ordering between routines that produce weakly-ordered results and routines that consume that data.</p>
<p>Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it is not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches specula-tively just before, during, or after the execution of an MFENCE instruction.</p>
<p>This instruction’s operation is the same in non-64-bit modes and 64-bit mode.</p>
<p>Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded by any opcode of the form 0F AE Fx, where x is in the range 0-7.</p>
<h2>Operation</h2>
<pre>Wait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible);</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>void _mm_mfence(void)</p>
<h2>Exceptions (All Modes of Operation)</h2>
<p>#UD</p>
<p>If CPUID.01H:EDX.SSE2[bit 26] = 0.</p>
<p>If the LOCK prefix is used.</p>
<p>1.</p>
<p>A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.</p></body></html>